1. Field of the Invention
The present invention relates generally to improving the performance of integrated circuit devices and, more particularly, to circuits that produce synchronized output signals.
2. Description of the Related Art
This section is intended to introduce the reader to various aspects of art which may be related to various aspects of the present invention which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Microprocessor-controlled integrated circuits are used in a wide variety of applications. Such applications include personal computers, vehicle control systems, telephone networks, and a host of consumer products. As is well known, microprocessors are complex integrated circuit devices that perform specific functions under the control of a software program. This program is stored in a memory device which is coupled to the microprocessor. Not only does the microprocessor access memory devices to retrieve the program instructions, but it also stores and retrieves data created during execution of the program in one or more memory devices.
There are a variety of different memory devices available for use in microprocessor-based systems. The type of memory device chosen for a specific function within a microprocessor-based system generally depends upon which features of the memory are best suited to perform the particular function. Memory manufacturers, such as the present assignee, provide an array of innovative fast memory chips for various applications, including dynamic random access memory (DRAM) and static random access memory (SRAM). DRAM is relatively inexpensive to produce compared to SRAM, but SRAM is typically operates at faster speeds. Additionally, DRAM usually must be continually refreshed or it will lose its data. SRAM on the other hand retains stored data as long as power is applied to it.
Although both DRAM and SRAM are making significant gains in speed and bandwidth, increases in the operating speeds of microprocessors necessitate ever-increasing performance requirements for memory devices of all types. Regardless of the type of memory, the solution for providing adequate memory bandwidth depends on many factors. Examples of such factors include the system architecture in which the memory is to be deployed, the design goals of the specific application, and the processor that is employed with the memory. All of these factors and a host of others contribute to the decision of which memory to use for a given application.
Obstacles to making memory chips faster include synchronization problems, signal delay within the chip, the package design, power consumption requirements, and the like. Many of these problems become more pronounced as desired operating speeds increase. Thus, significant research and development has been devoted to finding faster ways to access memory and to reduce or hide latency associated with memory accesses.
One type of memory device that may contribute to increased processing speeds in computer systems is the Synchronous Dynamic Random Access Memory (SDRAM). An SDRAM differs from a standard DRAM in that the SDRAM includes input and output latches to hold information from and for the processor. Data is strobed into or out of the SDRAM device in synchronization with the system clock. An SDRAM allows the system processor to save wait states because input information to the SDRAM (i.e., addresses, data, and controls signals) is latched, thus allowing the processor to perform other tasks while waiting for the SDRAM to finish its task of storing or retrieving relevant data. After a predetermined number of clock cycles during which the SDRAM is processing the processor's request, the processor may return to the SDRAM and obtain the requested information from the output latches.
A technique for increasing the speed of an SDRAM is to implement a Double Data Rate (DDR) SDRAM. In a DDR memory device, the data transfer rate is twice that of a regular memory device, because the input/output data of the DDR can be strobed twice for every clock cycle. That is, data is sent on both the rising and falling edges of the clock signal rather than just the rising edge of the clock signal as in typical Single Data Rate (SDR) systems. However, because the DDR technology utilizes both the rising and falling edges of the clock signal, problems may arise in obtaining proper setup and latch times for the data if an “unclean” clock signal is used. For example, the clock signal may become distorted or skewed as it passes through certain elements, i.e. input buffers. This may adversely affect the clock signal such that data latching times are not achieved.
In high speed memory devices such as DDR SDRAMs, the timing of the clock signal is important. The clock that is used to strobe the SDRAM is synchronized with other signals, which may be external to the SDRAM. Several known methods of synchronizing signals exist today. In one method, a delay locked loop (DLL) circuit is used. The DLL circuit creates an output signal that is matched in terms of frequency and/or phase to the input signal, which may be an external clock signal, for example. In DLL circuits, an input buffer receives an input signal and transmits the signal to a delay line. Generally, the delay line consists of a number of delay elements, such as inverters. The output signal from the delay line is compared to the input signal, and the number of delay elements is adjusted by a shift register or counter until the input and the output signals are equal.
A second known synchronization method utilizes a synchronous mirror delay (SMD) circuit which forces the input signal through a forward path delay line. However, the SMD circuit forces the output clock signal through a reverse path delay line as well. Similarly, the input signal and the output signal are compared, and adjustments to the delay lines are made until the input and output signal are equal.
Finally, a third known synchronization circuit may be referred to as a measure controlled delay (MCD). The MCD circuit measures the offset between the input signal and an output signal and adjusts a delay line to force the two signals into alignment.
However, the preceding synchronization circuits are incapable of producing a synchronous output signal with a different duty cycle from the input signal or producing a clean synchronous output signal based on an unclean input signal. As discussed previously, an unclean signal may not allow the proper latch times to be achieved for DDR components.